1. Field of the Invention
This invention relates generally to capacitor arrays and, more specifically, to a capacitor array layout technique which will improve capacitor array matching.
2. Description of the Prior Art
A successive approximation analog-to-digital (A/D) converter uses a binary weighted capacitor array. For a binary search algorithm, the ideal size of these capacitors must have the following ratios: the smallest capacitor has a single unit capacitance, the next one is two units, four units, eight units, and up to 2.sup.n-1 (n being the bit resolution of the A/D converter). This requires a capacitance of 1024 units for a 10-bit A/D with the largest capacitor having 512 units. In order to guarantee one-bit accuracy, the largest capacitor must be within (100.times.1/2.sup.n)% of the entire array. Otherwise, missing codes and system nonlinearities will be present.
Care must be taken when laying out the capacitor array. The capacitor array must be laid out in a way to avoid process variations. A popular way to do this is to lay out the capacitor array as a set of concentric capacitors with increasing radii based on the size of the capacitor (see FIG. 3A). Although good processing matching may be achieved, this configuration shows systematic mismatch errors.
Other matching methods may include active circuitry which calibrates the capacitor array to match the ideal ratios. Such methods may yield more accurate results, but are more costly in terms of silicon area, power consumption, and testing.
A passive way to obtain high capacitor matching is to place a small number of capacitors within a very small proximity. In addition, if a small number of capacitors are used, a thermometer code may be used to enable specific capacitors for minimizing process dependence and capacitor interaction to guarantee the presence of all codes. However, this process is very routing intensive, and does not guarantee accuracy.
Therefore, a need existed to provide an improved capacitor array arrangement. The improved capacitor array arrangement must be able to improve capacitor array matching. The improved capacitor array arrangement must be able to improve capacitor array matching in a cost effective manner (i.e., minimal amount of silicon area, power consumption, and testing). The improved capacitor array arrangement must be able to minimize mismatching due to fringe capacitance. The improved capacitor array arrangement must further be able to minimize process gradient dependence. The improved capacitor array arrangement must also be able to minimize mismatches due to macroscopic capacitor mismatches.